1. Field of the Invention
The present invention relates to a data transfer device comprising a plurality of data holding circuits connected in cascade.
2. Description of the Related Art
FIG. 1 shows the configuration of a data transfer circuit comprising primary flip-flops FF1-1 and FF1-2 that operate synchronously with first clock pulse signal CLK1, and secondary flip-flops FF2-1 and FF2-2 that operate synchronously with second clock pulse signal CLK2 asynchronous to the CLK1.
FIG. 2 is a timing chart showing an operation of the data transfer circuit shown in FIG. 1. As shown in FIG. 2, the primary flip-flops FF1-1 and FF1-2 hold input data D1-1 and D1-2 respectively at the rising timing of the first clock pulse signal CLK1 to output these as data D2-1 and D2-2 respectively. The secondary flip-flops FF2-1 and FF2-2 hold the data D2-1 and D2-2 output from the primary flip-flops FF1-1 and FF1-2 respectively at the rising timing of the second clock pulse signal CLK2 to output these as data D3-1 and D3-2 respectively.
For example, there is disclosed a date rate conversion circuit in a Japanese Patent Application Laid-Open Publication No. H02-180419.
FIG. 3 is a timing chart showing the operation of the data transfer circuit having the above configuration when a first clock pulse signal CLK1 and a second clock pulse signal CLK2 rise at substantially the same timing.
As shown in FIG. 3, the primary flip-flops FF1-1 and FF1-2 can hold data D1-1 and D1-2 respectively synchronously with the first clock pulse signal CLK1. Meanwhile, the data hold operation in the secondary flip-flops FF2-1 and FF2-2 becomes unstable because the timing at which the data D2-1 and D2-2 are output from the primary flip-flops substantially coincides with the rising timing of the second clock pulse signal CLK2. For example, it may be that the flip-flop FF2-1 cannot perform the hold operation synchronous with the second clock pulse signal CLK2 and continues to output the value held since before the CLK2 rose, whereas the flip-flop FF2-2 outputs the value that has got held synchronously with the second clock pulse signal CLK2. That is, with the conventional data transfer circuit, there is the problem that if clock pulse signals CLK1 and CLK2 contend, the outputs of the secondary flip-flops FF2-1 and FF2-2 may not match.